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NTHS5404T1
SOLDERING FOOTPRINT*
1
2.03 2
0.08
1
2.03 2
0.08
1.72 7
2.36 2
0.093
0.63 5
0.025
2.36 2
0.093
0.068
PITCH
8X
0.45 7
0.018
Figure 12. Basic
8X
0.66
0.026
mm
inches
2X
0.45 7
0.018
2X
0.66
0.026
Figure 13. Style 1 and 4
mm
inches
ADDITIONAL SOLDERING FOOTPRINTS*
1
2.03 2
0.08
2.03 2
0.08
2X
0.66
4X
0.45 7
0.018
2X
1.09 2
0.043
1
0.026
1.09 2
0.043
2.36 2
0.63 5
0.025
PITC H
0.093
0.63 5
0.025
PITCH
2.36 2
0.093
4X
0.66
0.026
Style 2
2X
1.118
0.044
mm
inches
2X
0.45 7
0.018
1.118
0.044
Style 3
mm
inches
*For additional information on our Pb ? Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 12. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area,
particularly for the drain leads.
The minimum recommended pad pattern shown in
Figure 13 improves the thermal area of the drain
confines of the basic footprint. The drain copper area is
0.0054 sq. in. (or 3.51 sq. mm). This will assist the power
dissipation path away from the device (through the copper
lead ? frame) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
connections (pins 1, 2, 3, 6, 7, 8) while remaining within the
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